The following invention relates to a clock regeneration circuit employing a digital phase locked loop for phase locking a clock to both a data signal and a second signal which may be a synchronization signal.
In a thin film electroluminescent (TFEL) display, light is emitted at pixel points in a predetermined scanning sequence. In order to generate light at these pixel points at the appropriate time, video data must be synchronized with both an internal clock and horizontal and vertical synchronization. One need with such displays is to create clock pulses that are synchronized to both the edges of the horizontal sync and data pulses from the video input source. The clock's primary purpose is to ensure that the video data is placed in the correct pixel location. Lack of phase synchronization between the data and the internal clock causes noise in the display because the appropriate pixel is not turned on at the right time.
Conventionally, phase locked loops have been used to synchronize internal clock generation to horizontal or vertical synchronization pulses. However, this technique did not include phase locking the data pulses to the internal clock. Also, conventional analog-type phase locked loops can be noisy and often require specialized parts. Most phase locked loops for conventional systems must be finely adjusted to correct for variations that can occur in production. Analog phase locked loops are also sensitive to temperature changes which can be problematical in viewing devices such as TFEL panels which require large voltages and generate heat. Further, to achieve an accuracy level as low as one-fourth pixel, a high loop gain, which would tend to make the phase locked loop unstable, would be required.